TM56F1552

1.	ROM: 4K x 16 bits Flash Program Memory
2.	EEPROM: 128 x 8 bits
3.	RAM: 336 x 8 bits
4.	STACK: 8 Levels
5.	System Clock type selections:
	Fast clock from 1~20 MHz Crystal (FXT)
	Fast clock from Internal RC (FIRC, 16 MHz)
	Slow clock from 32768 Hz Crystal (SXT)
	Slow clock from Internal RC (SIRC, 85 KHz@VCC=5V)
6.	System Clock Prescaler:
	System Clock can be divided by 1/2/4/8 option
7.	Power Saving Operation Mode
	FAST Mode: Slow-clock is enabled, Fast-clock keeps CPU running
	SLOW Mode: Fast-clock can be disabled or enabled, Slow-clock keeps CPU running
	IDLE Mode: Fast-clock and CPU stop. Slow-clock, T2, or Wake-up Timer keep running
	STOP Mode: All clocks stop, T2 and Wake-up Timer stop
8.	3 Independent Timers
	Timer0
-	8-bit timer divided by 1~256 pre-scale option / auto-reload / counter / interrupt / stop function
	Timer1
-	8-bit timer divided by 1~256 pre-scale option / auto-reload / interrupt / stop function
-	Overflow and Toggle out
	T2
-	15-bit timer with 4 interrupt interval time options
-	IDLE mode wake-up timer or used as one simple 15-bit time base
-	Clock source: Slow-clock, Fsys/128, or FIRC/512 (16 MHz/512)
 
9.	Interrupt
	Three External Interrupt pins
-	1 pin is falling edge wake-up triggered & Interrupts
-	2 pins are rising or falling edge wake-up triggered & Interrupt
	Timer0 / Timer1 / T2 / Wake-up Timer Interrupt
	ADC Interrupt
	Comparator  Interrupt
	PWM Interrupt
	Touch Key Interrupt
	LVD Interrupt
10.	Wake-up Timer (WKT)
	Clocked by built-in RC oscillator with 4 adjustable interrupt times
-	12 ms / 24 ms / 48 ms / 96 ms @VCC=5V
11.	Watchdog Timer (WDT)
	Clocked by built-in RC oscillator with 4 adjustable reset times
-	96 ms / 192 ms / 768 ms / 1536 ms @VCC=5V
	Watchdog timer can be disabled / enabled in STOP mode
12.	Six 16 bits PWMs
	Six individual duty-adjustable, shared period-adjustable
	PWM clock source: System clock (Fsys), FIRC (16 MHz), FIRC*2 (32 MHz)
	PWM0 supports complementary output (PWM0P, PWM0N)
	PWM0 output with non-overlap time durations adjustable: (0~15)*(PWMCLK)
13.	12-bit ADC with 14 channels External Pin Input and 3 channels Internal Voltage Channel
	Three internal voltage channel: VBG, 1/4VCC, OPO
	ADC reference voltage: VCC, VBG (2.48V)
14.	Touch Key (TM56F1552/52T only)
	15 channels Touch Key with 1 external CLD
	1 internal reference capacitor
15.	Operational Amplifier and Comparator
	Operational Amplifier x 1
	Comparator x 1
-	With 7-bit DAC input
-	DAC reference voltage: VCC or VBG (1.20V or 2.48V)
 
16.	Reset Sources
	Power On Reset
	Watchdog Timer Reset
	Low Voltage Reset
	External Pin Reset
17.	Low Voltage Reset (LVR) and Low Voltage Detection (LVD)
	16-Level Low Voltage Reset: 2.05V ~ 4.15V, can be disabled
	15-Level Low Voltage Detection: 2.20V ~ 4.15V, can be disabled
18.	Operating Voltage
	Fsys= 16 MHz, 1.9V~5.5V @LVR disable/25*C. Suggest LVR ≥ 2.20V at -40*C to +105*C
Note: Power-up VCC must exceed POR 1.95V and user selected LVR level, refer to the “Electrical Characteristics Graphs” to avoid entering ROM dead zone.
19.	Operating Temperature Range : -40°C to + 105°C
20.	Table Read Instruction: 16-bit ROM data lookup table
21.	Integrated 16-bit Cyclic Redundancy Check (CRC) function
22.	Instruction set: 39 Instructions
23.	I/O ports:
	Maximum 18 programmable I/O pins
-	Open-Drain Output
-	CMOS Push-Pull Output
-	Schmitt Trigger Input with pull-up / pull-down resistor option
-	All I/O with High-Sink
-	1/2 VCC (1/2 bias) Output
24.	Programming connectivity support 4-wire (ICP) or 7-wire program
25.	Package Types:
	20-pin SOP (300 mil)
	16-pin SOP (150 mil)
	20-pin QFN (3x3x0.75-0.4 mm) (L=0.25 mm)
	20-pin TSSOP (173 mil)
26.	On-chip Debug/ICE Interface
	Use PB0/PB3 Pins