FEATURES1. ROM: 4K x 16 bits MTP(TM56M1522/22B/22C), 2K x 16 bits MTP(TM56M1521H)
2. RAM: 256 x 8 bits
3. STACK: 8 Levels
4. System Clock type selections:
Fast clock from 1~20 MHz Crystal (FXT)
Fast clock from Internal RC (FIRC, 16 MHz)
Slow clock from 32768 Hz Crystal (SXT)
Slow clock from Internal RC (SIRC, 95 KHz@VCC=5V)
5. System Clock Prescaler:
System Clock can be divided by 1/2/4/8 option
6. Power Saving Operation Mode
FAST Mode: Slow-clock is enabled, Fast-clock keeps CPU running
SLOW Mode: Fast-clock can be disabled or enabled, Slow-clock keeps CPU running
IDLE Mode: Fast-clock and CPU stop. Slow-clock, T2, or Wake-up Timer keep running
STOP Mode: All clocks stop, T2 and Wake-up Timer stop
7. 3 Independent Timers
Timer0
- 8-bit timer divided by 1~256 pre-scale option / auto-reload / counter / interrupt / stop function
Timer1
- 8-bit timer divided by 1~256 pre-scale option / auto-reload / interrupt / stop function
- Overflow and Toggle out
T2
- 15-bit timer with 4 interrupt interval time options
- IDLE mode wake-up timer or used as one simple 15-bit time base
- Clock source: Slow-clock, Fsys/128, or FIRC/512 (16 MHz/512)
8. Interrupt
Three External Interrupt pins
- 1 pin is falling edge wake-up triggered & Interrupts
- 2 pins are rising or falling edge wake-up triggered & Interrupt
Timer0 / Timer1 / T2 / Wake-up Timer Interrupt
ADC Interrupt
Comparator Interrupt
PWM Interrupt
LVD Interrupt
9. Wake-up Timer (WKT)
Clocked by built-in RC oscillator with 4 adjustable interrupt times
- 10.5 ms / 21 ms / 42 ms / 84 ms @VCC=5V
10. Watchdog Timer (WDT)
Clocked by built-in RC oscillator with 4 adjustable reset times
- 84 ms / 168 ms / 672 ms / 1344 ms @VCC=5V
Watchdog timer can be disabled / enabled in STOP mode
11. Six 16 bits PWMs
Six individual duty-adjustable, shared period-adjustable
PWM clock source: System clock (Fsys), FIRC (16 MHz), FIRC*2 (32 MHz)
PWM0 supports complementary output (PWM0P, PWM0N)
PWM0 output with non-overlap time durations adjustable: (0~15)*(PWMCLK)
PWM0N/0P/1/2/3/5 has two outputs(PWM4 merely one)
12. 12-bit ADC with 13 channels for External Pin Input and 2 channels for Internal Voltage
Two internal voltage channels: VBG, 1/4VCC
ADC reference voltage: VCC, VBG (2.48V) and VBG (2V)
13. Comparator
Comparator x 1
- With 7-bit DAC input
- DAC reference voltage: VCC or VBG (1.20V or 2.48V)
14. Reset Sources
Power On Reset
Watchdog Timer Reset
Low Voltage Reset
External Pin Reset
15. Low Voltage Reset (LVR) and Low Voltage Detection (LVD)
16-Level Low Voltage Reset: 2.05V~4.15V(TM56M1522/22B/21H)/1.8V~3.9V(TM56M1522C), can be disabled
15-Level Low Voltage Detection: 2.20V~4.15V(TM56M1522/21H)/1.93V~3.87V(TM56M1522B/22C), can be disabled
16. Operating Voltage
Fsys= 16 MHz, LVR~5.5V. Suggest LVR ≥ 2.30V
Fsys= 8 MHz, PWMCKS=FIRC*1, LVR~5.5V. Suggest LVR ≥ 2.05V(TM56M1522/22B/21H)
Fsys= 8 MHz, PWMCKS=FIRC*1, LVR~5.5V. Suggest LVR ≥ 1.8V(TM56M1522C)
Note: Refer to the “Electrical Characteristics Graphs”.
17. Operating Temperature Range : -40°C to + 105°C
18. Table Read Instruction: 16-bit ROM data lookup table
19. Integrated 16-bit Cyclic Redundancy Check (CRC) function
20. Instruction set: 39 Instructions
21. I/O ports:
Maximum 14 programmable I/O pins
- Open-Drain Output
- CMOS Push-Pull Output
- Schmitt Trigger Input with pull-up / pull-down resistor option
- All I/O with High-Sink
- 1/2 VCC (1/2 bias) Output
All pin change wake up (falling edge and rising edge trigger)
22. LDOC
1.2V LDO regulator @Max 70mA output to PA3
23. IRCFT
FIRC frequency 5-bit fine-tuning per trimming step for frequency tracking
24. 2V ADC Vref
25. Programming connectivity support 5-wire (ICP) or 8-wire program
26. RDCTL: Read signal delay control for Program ROM
The user must switch this register to “8ns” to enhance the performance of minimal operating voltage.
27. Trimmed VBG1.2V/2V
The users could move BG2TRIM to BGTRIM for exact 2V VBG.
28. Package Types:
16-pin SOP (150 mil)
10-pin MSOP (118 mil)
8-pin SOP (150 mil)
16-pin QFN (3*3*0.75 - 0.5mm)
10-pin DFN (3*3*0.75 - 0.5mm)
29. Supported EV board
TM56F1552/22