TM89P55M

1. Low power dissipation. 
 1.5V/3V operating voltage range. 
2. Powerful instruction set. 
 Binary addition, subtraction, BCD adjustment. BCD can be executed 
  directly in addition, subtraction operation. 
 4 bits x 4 bits Multiplier 
 Single-bit manipulation (set, reset, decision for branch). 
 Various conditional branches. 
 16 initial working registers and manipulators. (can be extended to all RAM 
  by Page Mode) 
 Table look-up. 
 LCD driver data transfer. 
3. ROM capacity. 16K x 16 bits. 
 Instructon ROM Max. cpacity 16K x 16 bits. 
 Table ROM Max. capacity 24K/12K x 8/16 bits. 
4. RAM capacity. 4K/2K/1K x 4/8/16 bits. 
 LCD Max. capacity 256/128/64 x 4/8/16 bits. 
 STACK Max. capacity 16 x 16 bits. 
 HL/ZR store Max. capacity 16/16 x 16 bits. 
5. With direct/index addressing mode in data RAM access. 
6. LCD driver output. 
 Max 960 LCD dots by 16common outputs and 60 segment outputs. 
 COM12~16 can be defined as SEG64~61 by option. 
 SEG41~60 can be defined as 
  IOB1~4,KI1~4,ELC,ELP,BZB,BZ,IOD1~4,IOC1~4 by option. 
 1/4~1/16 Duty can be selected by option. 
 1/3 ~1/5 Bias can be selected by option. 
 Single instruction to turn off all segments. 
 COM5~16 can be defined as CMOS or P_open drain type output by option. 
 External regulator mode for VL1/2 by option. 
7. Input/output ports. 
 Port IOA 4 pins (with internal pull-low, input signal chattering 
  prevention circuitry), and can be defined as CX,RFC0~2 by option. 

 Port IOB 4 pins (with internal pull-low), and can be defined as SEG41~44 
  by option. 
 Port IOC 4 pins (with internal pull-low, low-level-hold, input signal 
  chattering prevention circuitry), and can be defined as SEG57~60 by option. 
 Port IOD 4 pins (with internal pull-low, input signal chattering prevention 
  circuitry), and can be defined as SEG53~56 by option. 
 Port IOE 4 pins (with internal pull-low), and can be defined as RFC3~5,CX2 
  by option. 
8. Interrupt function. 
 External factors 5 (INT pin, Port IOA, IOC, IOD & KI input). 
 Internal factors 5 (Pre-Divider, Timer1, Timer2, Timer3 & RFC). 
9. Built-in EL-light driver. 
 ELC, ELP. Can be defined as SEG49,50 by option. 
10. Built-in Alarm, clock or single tone melody generator. 
 BZB, BZ. Can be defined as SEG51,52 by option. 
11. Built-in resistance to frequency converter. 
 CX,RFC0~5,CX2. Can be defined as IOA1~4,IOE1~4 by option. 
12. Built-in key matrix scanning function. 
 KO1~KO16(Shared with SEG1~16) 
 KI1~KI4. Can be defined as SEG45~48 by option. 
13. Three 6-bit programmable timer with programmable clock source. 
 Read out the content in anytime 
 Merged 2 or 3 timers as 12-bit or 18-bit timer 
 Used as counter for RFC 
14. Watchdog timer. 
15. Built-in voltage charge halver & pump circuit. 
16. Dual clock operation 
 slow clock oscillation can be defined as X’tal or external RC type oscillator 
  by option. 
 fast clock oscillation can be defined as 3.58MHz ceramic resonator, internal 
  R or external R type oscillator by option. 
17. HALT function. 
18. STOP function.

Timer / Calendar / Calculator / Thermometer