GENERAL DESCRIPTIONThis chip is 2nd-order Sigma-delta ADC with switch-capacitor PGIA. So it
includes a low drift, low noise PGIA and 2nd-order S-D ADC about 14 bits
resolution. Also it has a temperature sensor. This chip has many modes
of input channel can be set. And PGIA also has selectable gains of 1x, 2x,
4x, 8x, 16x, 32x, 64x, 128x to accommodate these applications. It also
has the system calibration mechanism for eliminating the system offset.
Above input channel mode, gain-select, calibration mechanism and etc.
can be set by SYS/ADC registers through I2C interface.
FEATURES1. Operation range:
. Digital voltage range: 2.4 to 3.6V.
. Analog voltage range: 2.4 to 3.6V.
. Operation current consumption:
(i)Normal operation: 1.5 mA (ADC clock frequency is 81.92 kHz ,and fcv=10Hz).
(ii)Low power operation: <1 mA (utilize register EN_BGR=0: external in and <1.2V).
2. 16-bit Sigma-Delta ADC:
. Embedded 3 differential input channels.
. Built-in PGA, selected gains are 1X, 2X, 4X, 8X, 16X, 32X, 64X, 128X.
. Clock frequency is selected by external XTAL circuit or internal RC OSC.
. Conversion rate is 10 SPS when clock frequency is 81.92 kHz. It
could be tuned by clock frequency in (50/60 rejection function
works at ADC clock frequency, is 81.92 kHz).
. RMS noise is 250 nV at conversion rate, is 10 SPS, Gain is 128X.
. NFB (noise-free bit) is 14 bits (Gain=128X, REFP=2V).
3. Built-in LDO for AVDD out:
. VDDO/LDO’s level is selected by SAVDD[1:0] registers.
. LDO AVDD’s out level is 2.4V/2.6V/2.9V.
. LDO AVDD's driving capability is about 10 mA.
4. Internal bias current can be selected or not.
. Built-in band-gap reference provider or out-chip bias.
5. Temperature sensor precision +/-5 degree C (after calibration).
6. I2C interface.
7. Application: (with offset calibration)
. Weight scale.
. Strain Gauge.
. Pressure Scale.