FEATURES1. ROM: 1K x 14 bits MTP (Multi Time Programmable ROM)
2. RAM: 96 x 8 bits
3. STACK: 6 Levels
4. System Oscillation Sources (Fsys) :
. Fast-clock
- FIRC (Fast Internal RC): 8MHz / 4MHz / 2.667MHz / 2MHz
. Slow-clock
- SIRC (Slow Internal RC): 128 KHz / 32 KHz / 8 KHz / 2 KHz @VCC=3V
5. Dual System Clock :
. FIRC + SIRC
6. Power Saving Operation Mode
. FAST Mode: Slow-clock can be disabled or enabled, Fast-clock keeps CPU running
. SLOW Mode: Fast-clock can be disabled or enabled, Slow-clock keeps CPU running
. IDLE Mode: Fast-clock and CPU stop. Slow-clock, T2, or Wake-up Timer keep running
. STOP Mode: All Clocks stop, T2 and Wake-up Timer stop
7. 3 Independent Timers
. Timer0
- 8-bit timer divided by 1~256 pre-scaler option, Counter / Interrupt / Stop function
. Timer1
- 8-bit timer divided by 1~256 pre-scaler option, Reload / Interrupt / Stop function
- Overflow and Toggle out
. T2
- 15-bit timer with 4 interrupt interval time options
- IDLE mode wake-up timer or used as one simple 15-bit time base
- Clock source: Slow-clock (SIRC), Fsys/128
8. Interrupt
. Three External Interrupt pins
- 1 pin are falling edge wake-up triggered & interrupts
- 2 pins is rising or falling edge wake-up triggered & interrupt
. Timer0 / Timer1 / T2 / WKT (wake-up) Interrupts
9. Wake-up (WKT) Timer
. Clocked by built-in RC oscillator with 4 adjustable interrupt times
17 ms / 34 ms / 68 ms / 136 ms @VCC=3V , 16 ms / 32 ms / 64 ms / 128 ms @VCC=5V
10. Watchdog Timer
. Clocked by built-in RC oscillator with 4 adjustable reset times
140ms/280ms/1120ms/2240ms @VCC=3V , 128ms/256ms/1024ms/2048ms @VCC=5V
. Watchdog timer can be disabled/enabled in STOP mode (WDTSTP, R15.5)
11. 1 Independent PWM
. PWM0:
- 8+2 bits, duty-adjustable, period-adjustable controlled PWM
- PWM0 clock source: Fast-clock or IRC16M, with 1~64 pre-scalers
- With differential output pair
- Non-overlap durations adjustable
- PWMAP and PWMAN are high drive / sink pins
12. 12-bit ADC Converter with 8 input channels and 1 internal reference voltage
. Internal reference voltage LDO2.5V ±2% @ 25*C, VCC=3V~5V
13. Reset Sources
. Power On Reset / Watchdog Reset / Low Voltage Reset / External Pin Reset
14. Low Voltage Reset Option: LVR1.8V, LVR1.8 off in STOP mode
15. Operating Voltage:
. Fsys=1 MHz, 2.0 ~5.5V
. Fsys=4 MHz, 2.0~5.5V
. Fsys=8 MHz, 2.0~5.5V
16. Operating Temperature Range: -40°C to +85°C
17. Table Read Instruction: 14-bit ROM data lookup table.
18. Instruction set: 38 Instructions
19. Instruction Execution Time
. 2 oscillation clocks per instruction except branch
20. I/O ports: Maximum 13 programmable I/O pins
. Pseudo-Open-Drain Output (PA2~PA0)
. Open-Drain Output
. CMOS Push-Pull Output
. Schmitt Trigger Input with pull-up resistor option
21. Programming connectivity support 5-wire (ISP) or 8-wire program.
22. Package Types:
. SOP-16/DIP-16
23. Supported EV board on ICE
. EV board: EV8205